US 12,265,711 B1
Mechanism to enhance endurance in universal flash storage devices
Ashwini Pandey, Muzaffarpur (IN); Pratibind Kumar Jha, Hyderabad (IN); and Manish Garg, Hyderabad (IN)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Jan. 15, 2024, as Appl. No. 18/412,776.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0616 (2013.01) [G06F 3/0629 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method performed by a universal flash storage (UFS) device of a computing device for configuring flash memory cells, comprising:
setting a number of degraded triple-level cells (TLCs) attribute; and
configuring at least one degraded triple-level cell (TLC) as at least one single-level cell (SLC) based on the number of degraded TLCs attribute, the at least one degraded TLC being not functional as a TLC and functional as an SLC.