US 12,265,710 B2
Memory management procedures for write boost mode
Xing Wang, Shanghai (CN); Zhen Gu, Shanghai (CN); Xu Zhang, Shanghai (CN); and Liping Xu, Shanghai (CN)
Assigned to Micron Technology, Inc., Boise, ID (US)
Appl. No. 17/630,113
Filed by Micron Technology, Inc., Boise, ID (US)
PCT Filed Mar. 16, 2021, PCT No. PCT/CN2021/081074
§ 371(c)(1), (2) Date Jan. 25, 2022,
PCT Pub. No. WO2022/193129, PCT Pub. Date Sep. 22, 2022.
Prior Publication US 2023/0359365 A1, Nov. 9, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0616 (2013.01) [G06F 3/0634 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A memory system, comprising:
one or more memory devices; and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
receive, from a host system, a command to write data to the one or more memory devices;
receive a signal to activate a write booster mode of the one or more memory devices;
write the data to a first location of the one or more memory devices using a first mode for storing one bit per memory cell in response to receiving the command from the host system to write the data and receiving the signal to activate the write booster mode;
select a first portion of the data to rewrite to the one or more memory devices using a second mode for storing three or more bits per memory cell in response to one or more parameters satisfying one or more thresholds;
rewrite the first portion of the data to a second location of the one or more memory devices using the second mode in response to selecting the first portion of the data and receiving the signal to activate the write booster mode; and
maintain a second portion of the data at the first location of the one or more memory devices in response to the one or more parameters satisfying the one or more thresholds.