US 12,265,706 B2
Memory system with nonvolatile semiconductor memory
Hiroshi Yao, Kanagawa (JP); Shinichi Kanno, Tokyo (JP); and Kazuhiro Fukutomi, Tokyo (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Dec. 26, 2023, as Appl. No. 18/396,352.
Application 18/396,352 is a continuation of application No. 18/155,282, filed on Jan. 17, 2023, granted, now 11,893,238.
Application 18/155,282 is a continuation of application No. 17/643,034, filed on Dec. 7, 2021, granted, now 11,579,773, issued on Feb. 14, 2023.
Application 17/643,034 is a continuation of application No. 17/018,956, filed on Sep. 11, 2020, granted, now 11,216,185, issued on Jan. 4, 2022.
Application 17/018,956 is a continuation of application No. 16/044,257, filed on Jul. 24, 2018, granted, now 10,871,900, issued on Dec. 22, 2020.
Application 16/044,257 is a continuation of application No. 15/880,168, filed on Jan. 25, 2018, granted, now 10,055,132, issued on Aug. 21, 2018.
Application 15/880,168 is a continuation of application No. 15/391,184, filed on Dec. 27, 2016, granted, now 9,910,597, issued on Mar. 6, 2018.
Application 15/391,184 is a continuation of application No. 14/467,685, filed on Aug. 25, 2014, granted, now 10,877,664, issued on Dec. 29, 2020.
Application 14/467,685 is a continuation of application No. 13/038,681, filed on Mar. 2, 2011, granted, now 8,832,357, issued on Sep. 9, 2014.
Claims priority of application No. 2010-214221 (JP), filed on Sep. 24, 2010.
Prior Publication US 2024/0126433 A1, Apr. 18, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G06F 12/02 (2006.01)
CPC G06F 3/0604 (2013.01) [G06F 3/0634 (2013.01); G06F 3/0641 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 12/0246 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/1044 (2013.01); G06F 2212/214 (2013.01); G06F 2212/7201 (2013.01); G06F 2212/7205 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A memory system comprising:
a nonvolatile semiconductor memory comprising a plurality of blocks, each of the blocks comprising a plurality of memory cells, each of the memory cells configured to store i-bits data, i being equal to or larger than 2, and
a controller circuit configured to perform a write operation to the nonvolatile semiconductor memory in a first mode, wherein
the controller circuit is configured to perform the write operation in the first mode in response to a request from a host device,
the controller circuit is configured to read data from one of the blocks written in the first mode and write the read data to another one of the blocks in a second mode, as a first operation,
the controller circuit is configured to calculate a total amount of valid data stored in the memory system, the valid data being data assigned to logical addresses,
the controller circuit is configured to determine whether to perform the first operation based on a result of the calculation of the total amount of the valid data,
the controller circuit is configured to read data from one of the blocks written in the second mode and write the read data to another one of the blocks in the second mode, as a second operation,
only j-bits data is written into each of memory cells in the first mode,
j is smaller than i, and
k-bits data is written into each of memory cells in the second mode, k being larger than j and equal to or smaller than i.