	US 12,265,630 B2
	Row access strobe (RAS) clobber and row hammer failures using a deterministic protocol
Yang Lu, Boise, ID (US); Markus H. Geiger, Boise, ID (US); and Nathaniel J. Meier, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 26, 2023, as Appl. No. 18/160,293.
Claims priority of provisional application 63/303,550, filed on Jan. 27, 2022.
Prior Publication US 2023/0244793 A1, Aug. 3, 2023
Int. Cl. G06F 21/57 (2013.01); G06F 21/55 (2013.01); G11C 8/18 (2006.01); G11C 29/02 (2006.01); G11C 29/50 (2006.01); G11C 29/52 (2006.01)

CPC G06F 21/577 (2013.01) [G06F 21/554 (2013.01); G11C 8/18 (2013.01); G11C 29/022 (2013.01); G11C 29/50004 (2013.01); G11C 29/52 (2013.01); G06F 2221/034 (2013.01); G11C 2029/5002 (2013.01)]

16 Claims

1. A memory device comprising:

at least one memory including a plurality of memory cells disposed in rows and columns; and

a controller, communicatively coupled to the at least one memory;

wherein the controller maintains data integrity in the at least one memory by executing a deterministic protocol; and

wherein the deterministic protocol is executed in conjunction with a base protocol configured for native failure risk mitigation, the base protocol including a probabilistic protocol, wherein the base protocol executed by the controller is configured to mitigate a risk of failure selected from the set of risk of failures consisting of a Row Hammer (RH) risk failure, a RAS Clobber risk failure, and a directed refresh management risk (DRFM) failure and when the risk failure is a RH risk failure, the deterministic protocol is configured to mitigate a RH1 risk (+/1 rows), a RH2 risk (+/−2 rows), a RAS clobber risk, and an inverse hammer risk.