| CPC G06F 13/4063 (2013.01) [H05K 1/0298 (2013.01)] | 22 Claims |
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1. A circuit, comprising:
a printed circuit board (PCB) that includes:
a closed loop data bus line having a first plurality of connections;
a closed loop address bus line having a second plurality of connections; and
a plurality of integrated circuits (ICs) each disposed on the closed loop data bus line at a respective connection of the first plurality of connections and on the closed loop address bus line at a respective connection of the second plurality of connections, wherein the plurality of ICs includes (i) a plurality of static random-access memory (SRAM) components configured to drive signals on the closed loop data bus line and the closed loop address bus line and (ii) a field programmable gate array (FPGA), wherein the closed loop data bus line and the closed loop address bus line are configured to prevent signal reflection, and wherein there are no termination resistors at any terminations to reduce size, weight, and/or part count of the circuit.
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