US 12,265,484 B2
Processing device and method of sharing storage between cache memory, local data storage and register files
Maxim V. Kazakov, San Diego, CA (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Sep. 3, 2021, as Appl. No. 17/467,104.
Prior Publication US 2023/0069890 A1, Mar. 9, 2023
Int. Cl. G06F 13/16 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 12/0875 (2016.01)
CPC G06F 13/1668 (2013.01) [G06F 9/30098 (2013.01); G06F 9/3887 (2013.01); G06F 9/3888 (2023.08); G06F 12/0875 (2013.01); G06F 2212/452 (2013.01)] 16 Claims
OG exemplary drawing
 
1. An accelerated processing device comprising:
a plurality of compute units each comprising:
a plurality of single-instruction-multiple-data (SIMD) units each comprising a register file;
a cache memory that is accessible to each of the SIMD units; and
local data storage (LDS) that is accessible to each of the SIMD units,
wherein the compute units are configured to:
dynamically allocate a respective register file of one or more of the plurality of SIMD units between at least one of the cache memory and the LDS during execution of an application in response to a request to execute the application on the plurality of compute units.