US 12,265,483 B2
Shunt-series and series-shunt inductively peaked clock buffer, and asymmetric multiplexer and de-multiplexer
Sandipan Kundu, Hillsboro, OR (US); Jihwan Kim, Portland, OR (US); Ajay Balankutty, Hillsboro, OR (US); Bong Chan Kim, Hillsboro, OR (US); Yutao Liu, Hillsboro, OR (US); and Frank O'Mahony, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 3, 2021, as Appl. No. 17/338,479.
Claims priority of provisional application 63/120,646, filed on Dec. 2, 2020.
Prior Publication US 2022/0171718 A1, Jun. 2, 2022
Int. Cl. G06F 13/42 (2006.01); G06F 1/04 (2006.01); G06F 13/16 (2006.01); H03K 17/687 (2006.01); H03K 19/20 (2006.01)
CPC G06F 13/1668 (2013.01) [G06F 1/04 (2013.01); G06F 13/4282 (2013.01); H03K 17/6872 (2013.01); H03K 19/20 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first driver to receive a first input and having a first driver output;
a second driver to receive a second input and having a second driver output, wherein the first input is complementary of the second input;
a first shunt-series set of inductors coupled to the first driver output; and
a second shunt-series set of inductors coupled to the second driver output, wherein the first shunt-series set of inductors is coupled to the second shunt-series set of inductors via a switch, wherein the first shunt-series set of inductors includes: (i) a first inductor coupled between the first driver output and the switch, and (ii) a second inductor coupled between the first driver output and a first output node.