| CPC G06F 12/1018 (2013.01) [G06F 12/084 (2013.01); G06F 12/1036 (2013.01); G06F 30/392 (2020.01); G06F 2212/622 (2013.01); G06F 2212/651 (2013.01)] | 20 Claims |
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1. An apparatus, comprising:
first and second client circuits configured to request to access a private memory space;
memory allocation circuitry configured to map private memory pages in the private memory space to a virtual address space;
cache circuitry configured to cache page table information corresponding to the mapped private memory pages, wherein the cached page table information is accessible to both the first and second client circuits; and
memory management circuitry configured to translate addresses in the virtual address space to addresses in a physical memory space.
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