US 12,265,470 B1
Bypassing cache directory lookups for processing-in-memory instructions
Travis Henry Boraten, Austin, TX (US); Jagadish B. Kotra, Austin, TX (US); and David Andrew Werner, Austin, TX (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Sep. 29, 2023, as Appl. No. 18/374,969.
Int. Cl. G06F 12/0815 (2016.01)
CPC G06F 12/0815 (2013.01) [G06F 2212/621 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a processing-in-memory component;
a cache system;
a cache coherence controller; and
a processor core configured to:
generate a processing-in-memory request with an indication that a memory address associated with the processing-in-memory request is clean or dirty; and
responsive to the indication being dirty, cause the cache coherence controller to perform a cache directory lookup for the memory address; or
responsive to the indication being clean, cause the processing-in-memory component to execute the processing-in-memory request.