US 12,265,440 B2
System, apparatus and method for loose lock-step redundancy power management
Efraim Rotem, Haifa (IL); Eliezer Weissmann, Haifa (IL); Doron Rajwan, Rishon Le-Zion (IL); Nir Rosenzweig, Givat Ella (IL); and Yoni Aizik, Haifa (IL)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Aug. 24, 2023, as Appl. No. 18/455,008.
Application 18/455,008 is a continuation of application No. 17/824,984, filed on May 26, 2022, granted, now 11,740,682.
Application 17/824,984 is a continuation of application No. 17/210,759, filed on Mar. 24, 2021, granted, now 11,402,891, issued on Aug. 2, 2022.
Application 17/210,759 is a continuation of application No. 16/663,645, filed on Oct. 25, 2019, granted, now 10,990,154, issued on Apr. 27, 2021.
Application 16/663,645 is a continuation of application No. 16/546,441, filed on Aug. 21, 2019, granted, now 10,963,034, issued on Mar. 30, 2021.
Application 16/546,441 is a continuation of application No. 15/635,307, filed on Jun. 28, 2017, granted, now 10,429,919, issued on Oct. 1, 2019.
Prior Publication US 2023/0393641 A1, Dec. 7, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/00 (2006.01); G06F 1/324 (2019.01); G06F 1/3296 (2019.01)
CPC G06F 1/324 (2013.01) [G06F 1/3296 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first core comprising:
a fetch circuit to fetch instructions;
a decode circuit to decode the instructions;
an execution circuit to execute arithmetic and logic operations;
a second core comprising:
a second fetch circuit to fetch instructions;
a second decode circuit to decode the instructions;
a second execution circuit to execute arithmetic and logic operations,
wherein in a first mode the first core and the second core are to operate at a common frequency, and in a second mode the first core and the second core are to operate at independent frequencies;
memory to store a first indicator, the first indicator to have a first value to indicate that the first core and a second core are to execute in the first mode to redundantly execute a first task at the common frequency; and
a controller to cause the first core and the second core to operate in the second mode at the independent frequencies, and thereafter operate in the first mode at the common frequency to redundantly execute the first task based at least in part on the first value of the first indicator.