US 12,265,439 B2
Co-existence of full frame and partial frame idle image updates
Seh Kwa, Saratoga, CA (US); Nausheen Ansari, Folsom, CA (US); and Sameer Kp, Bangalore (IN)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Apr. 22, 2022, as Appl. No. 17/726,639.
Application 17/726,639 is a continuation of application No. 15/858,055, filed on Dec. 29, 2017, granted, now 11,314,310.
Prior Publication US 2023/0064642 A1, Mar. 2, 2023
Int. Cl. G06F 1/32 (2019.01); G06F 1/3218 (2019.01); G06F 1/3234 (2019.01); G09G 5/36 (2006.01); G09G 5/393 (2006.01); G09G 5/395 (2006.01)
CPC G06F 1/3218 (2013.01) [G06F 1/3234 (2013.01); G06F 1/3265 (2013.01); G09G 5/363 (2013.01); G09G 5/393 (2013.01); G09G 5/395 (2013.01); G09G 2330/021 (2013.01); G09G 2330/022 (2013.01); G09G 2340/0435 (2013.01); G09G 2360/12 (2013.01); G09G 2360/18 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A display panel comprising:
a receiver to:
receive, from a transmitter and after a first frame boundary, a first packet comprising a symbol that indicates that a frame update is not expected; and
receive, from the transmitter and after a second frame boundary, a second packet comprising a symbol that indicates that a frame update is not expected, wherein the second frame boundary is the next frame boundary after the first frame boundary; and
a display controller to initiate one or more power management functions based on a value of the symbol in the first packet, wherein to initiate the one or more power management functions comprises to gate a clock signal for one or more components of the display panel.