| CPC G06F 1/3206 (2013.01) [G06F 1/08 (2013.01); G06F 1/3234 (2013.01); H04W 52/02 (2013.01)] | 20 Claims |
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1. A system on a chip (SOC), comprising:
an interface circuit comprising a plurality of devices configured to transfer packets between the SOC and one or more other SOCs external to the SOC, wherein the SOC and external SOCs are individually implemented on respective semiconductor dies, wherein the semiconductor die of the SOC is coupled with the semiconductor dies of the external SOCs via one or more serial communication links, and wherein the plurality of devices is configured to interface the SOC with the serial communication links; and
a bridge circuit configured to control the interface circuit,
wherein the bridge circuit is configured to:
obtain an indication to cause a subset of the devices to transition from a regular state to a low power state; and
generate at least one signal for the subset of devices in response to the indication, and
wherein the interface circuit is configured to:
obtain the signal generated from the bridge circuit; and
transition the subset of devices from the regular state to the low power state according to the signal from the bridge circuit, and maintain another subset of the devices in the regular state.
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