	US 12,265,417 B2
	Configurable clock macro circuits and methods
Alexander Rusakov, Moscow (RU); Alexander Andreev, San Jose, CA (US); Eng Huat Lee, Bayan Lepas (MY); and Andrei Nikishin, Moscow (RU)
Assigned to Altera Corporation, San Jose, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 22, 2021, as Appl. No. 17/482,220.
Prior Publication US 2022/0004221 A1, Jan. 6, 2022
Int. Cl. G06F 1/10 (2006.01); G06F 30/327 (2020.01); H01L 23/538 (2006.01); H01L 27/02 (2006.01); H03K 19/0185 (2006.01)

CPC G06F 1/10 (2013.01) [G06F 30/327 (2020.01); H01L 23/5384 (2013.01); H01L 27/0207 (2013.01); H03K 19/018585 (2013.01)]

20 Claims

1. An integrated circuit comprising a clock macro circuit, wherein the clock macro circuit comprises:

first, second, and third latch circuits, wherein the first latch circuit is coupled to the second latch circuit;

a multiplexer circuit coupled to the second and third latch circuits; and

programmable vias that are programmed during fabrication of the integrated circuit to couple inputs of the clock macro circuit to the first latch circuit, the second latch circuit, the third latch circuit, and the multiplexer circuit, wherein the programmable vias are programmed to cause the clock macro circuit to function as a selected type of clock circuit.