US 12,265,416 B2
Low power and area clock monitoring circuit using a capacitor and constant current sink
Kedar Rajpathak, Santa Clara, CA (US); and Tezaswi Raja, Santa Clara, CA (US)
Assigned to NVIDIA Corporation, Santa Clara, CA (US)
Filed by NVIDIA Corporation, Santa Clara, CA (US)
Filed on Apr. 4, 2023, as Appl. No. 18/295,560.
Prior Publication US 2024/0338051 A1, Oct. 10, 2024
Int. Cl. G06F 1/08 (2006.01); G06F 1/12 (2006.01)
CPC G06F 1/08 (2013.01) [G06F 1/12 (2013.01)] 41 Claims
OG exemplary drawing
 
1. A clock monitoring circuit for monitoring a clock signal, comprising:
a clock slow detection (CSD) circuit configured to assert a CSD signal when durations of phases of the clock signal lengthen, wherein the CSD circuit comprises:
two pairs of transistors, each pair connected in series and a first capacitor connected to a connection between a first pair of the two pairs of transistors and to a voltage reference and a second capacitor connected to a connection between a second pair of the two pairs of transistors and the voltage reference;
a third capacitor connected to drains of a second transistor of each of the two pairs of transistors and to the voltage reference;
a constant current sink connected to the drains of the second transistor of each of the two pairs of transistors and to the voltage reference; and
an inverter coupled to the third capacitor and constant current sink; wherein:
a voltage supply is connected to a source of a first transistor of each of the two pairs of transistors;
a non-inverted version of the clock signal is connected to gates of the first transistor of the first transistor pair and the second transistor of the second transistor pair; and
an inverted version a of the clock signal is connected to gates of the second transistor of the first transistor pair and the first transistor of the second transistor pair.