US 12,265,380 B2
Matching process controllers for improved matching of process
James Robert Moyne, Canton, MI (US); and Jimmy Iskandar, Fremont, CA (US)
Assigned to Applied Materials, Inc., Santa Clara, CA (US)
Filed by Applied Materials, Inc., Santa Clara, CA (US)
Filed on Dec. 30, 2020, as Appl. No. 17/137,679.
Application 17/137,679 is a continuation of application No. 15/444,647, filed on Feb. 28, 2017, granted, now 10,884,400.
Application 15/444,647 is a continuation of application No. 14/223,780, filed on Mar. 24, 2014, granted, now 9,606,519, issued on Mar. 28, 2017.
Claims priority of provisional application 61/890,802, filed on Oct. 14, 2013.
Prior Publication US 2021/0116898 A1, Apr. 22, 2021
Int. Cl. G03F 7/00 (2006.01); F27B 17/00 (2006.01); G05B 13/04 (2006.01); G05B 19/418 (2006.01); H01L 21/66 (2006.01); H01L 21/67 (2006.01); H05K 3/00 (2006.01); C23C 16/00 (2006.01)
CPC G05B 19/41875 (2013.01) [F27B 17/0025 (2013.01); G03F 7/705 (2013.01); G03F 7/70608 (2013.01); G03F 7/70616 (2013.01); G03F 7/70625 (2013.01); G03F 7/7065 (2013.01); G05B 13/04 (2013.01); H01L 21/67155 (2013.01); H01L 21/67253 (2013.01); H01L 22/20 (2013.01); H05K 3/00 (2013.01); C23C 16/00 (2013.01); G03F 7/70633 (2013.01); G03F 7/70683 (2013.01); G05B 2219/2602 (2013.01); G05B 2219/31014 (2013.01); G05B 2219/32096 (2013.01); G05B 2219/32097 (2013.01); G05B 2219/45028 (2013.01); G05B 2219/45031 (2013.01); G05B 2219/45032 (2013.01); Y02P 80/10 (2015.11); Y02P 90/02 (2015.11); Y02P 90/80 (2015.11)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
identifying first parameters of a first processing chamber of a semiconductor fabrication facility, the first parameters comprising first input parameters and first output parameters;
identifying second parameters of a second processing chamber of the semiconductor fabrication facility, the second parameters comprising second input parameters and second output parameters;
generating, by a processing device based on the first parameters and the second parameters, composite parameters comprising composite input parameters comprising process conditions and composite output parameters comprising metrology values;
generating third parameters by adjusting the first parameters, wherein the third parameters more closely approximate the composite parameters than the first parameters;
generating fourth parameters by adjusting the second parameters, wherein the fourth parameters more closely approximate the composite parameters than the second parameters; and
fabricating first semiconductors in the first processing chamber based on the third parameters and fabricating second semiconductors in the second processing chamber based on the fourth parameters, wherein the fabricating of the first semiconductors in the first processing chamber based on the third parameters corresponds to lower yield loss than corresponding fabrication of corresponding semiconductors in the first processing chamber based on the first parameters, and the fabricating of the second semiconductors in the second processing chamber based on the fourth parameters corresponds to lower yield loss than respective fabrication of respective semiconductors in the second processing chamber based on the second parameters.