US 12,265,376 B2
Programmable delay line with glitch suppression
John Kenney, West Windsor, NJ (US)
Assigned to Analog Devices, Inc., Wilmington, MA (US)
Filed by Analog Devices, Inc., Wilmington, MA (US)
Filed on Nov. 14, 2022, as Appl. No. 18/055,088.
Application 18/055,088 is a division of application No. 17/093,311, filed on Nov. 9, 2020, granted, now 11,526,153.
Prior Publication US 2023/0070085 A1, Mar. 9, 2023
Int. Cl. H03K 5/15 (2006.01); G05B 19/4155 (2006.01); H03K 3/037 (2006.01); H03K 5/00 (2006.01)
CPC G05B 19/4155 (2013.01) [H03K 3/037 (2013.01); G05B 2219/34043 (2013.01); H03K 5/00 (2013.01); H03K 2005/00058 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A delay system, comprising:
a static phase offset (SPO) delay element to receive an input signal, the SPO delay element comprising:
a capacitor and transistor subassembly coupled an input of the SPO delay element, the capacitor and transistor subassembly to apply a delay to the input signal when the capacitor and transistor subassembly is conducting;
a buffer coupled to an output of the SPO delay element; and
a latch coupled to the buffer and to receive an output of the buffer as a trigger input, wherein an output of the latch is to control conduction of the capacitor and transistor subassembly; and
a shift register coupled to the SPO delay element, the shift register to provide a control word to the SPO delay element, wherein the control word defines a value of the output of the latch.