US 12,265,325 B2
Inverse lithography and machine learning for mask synthesis
Amyn A. Poonawala, Santa Clara, CA (US); Jason Jiale Shu, San Jose, CA (US); and Thomas Chrisptopher Cecil, Menlo Park, CA (US)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Sunnyvale, CA (US)
Filed on Jul. 31, 2023, as Appl. No. 18/228,509.
Application 18/228,509 is a division of application No. 17/102,180, filed on Nov. 23, 2020, granted, now 11,762,283.
Claims priority of provisional application 62/948,158, filed on Dec. 13, 2019.
Prior Publication US 2023/0375916 A1, Nov. 23, 2023
Int. Cl. G06N 20/10 (2019.01); G03F 1/36 (2012.01); G03F 1/70 (2012.01); G03F 1/76 (2012.01); G06F 30/33 (2020.01); G06F 30/39 (2020.01); G06N 3/08 (2023.01)
CPC G03F 1/70 (2013.01) [G03F 1/36 (2013.01); G03F 1/76 (2013.01); G06F 30/33 (2020.01); G06F 30/39 (2020.01); G06N 3/08 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
converting, by a processor, a design pattern for a semiconductor device to a pixel domain, to provide a converted design pattern;
providing the converted design pattern as input to a trained machine learning (ML) model;
performing, using the ML Model, a plurality of dilated convolutions relating to the converted design pattern;
inferring, using the ML model, a mask for use in manufacturing the semiconductor device, based on the plurality of dilated convolutions; and
converting the inferred mask from a level-set function to a polygon representation, wherein the level-set function defines contours of the inferred mask.