US 12,265,121 B2
Compression-based scan test system
Sandeep Jain, Noida (IN); Shalini Pathak, Gurgaon (IN); and Prateek Singh, Delhi (IN)
Assigned to STMicroelectronics International N.V., Geneva (CH)
Filed by STMicroelectronics International N.V., Geneva (CH)
Filed on May 23, 2023, as Appl. No. 18/322,336.
Prior Publication US 2024/0393393 A1, Nov. 28, 2024
Int. Cl. G01R 31/3181 (2006.01); G01R 31/3185 (2006.01)
CPC G01R 31/31813 (2013.01) [G01R 31/318536 (2013.01); G01R 31/318552 (2013.01)] 26 Claims
OG exemplary drawing
 
1. A method for operating a Pseudo-Random Pattern Generator (PRPG) based scan test system comprising:
generating test patterns using a Pseudo-Random Pattern Generator (PRPG), generating the test patterns comprising clocking the PRPG using a first clock signal;
loading the test patterns into a plurality of scan chains coupled to the PRPG;
shifting the loaded test patterns using a second clock signal;
modifying a bit distribution of the generated test patterns with respect to the plurality of scan chains comprising:
freezing at least one clock cycle of the first clock signal while the second clock signal is active, wherein freezing the at least one clock cycle of the first clock signal causes a same pattern output by the PRPG to be clocked into the plurality of scan chains, or
freezing at least one clock cycle of the second clock signal while the first clock signal is active, wherein freezing the at least one clock cycle of the second clock signal prevents a first pattern output by the PRPG from being clocked into the plurality of scan chains;
applying the test patterns to a circuit under test (CUT) through the plurality of scan chains; and
capturing response patterns generated by the CUT in the plurality of scan chains.