US 12,265,119 B2
Repackaging IC chip for fault identification
Chien-Yi Chen, Hsinchu (TW); Kao-Chih Liu, Changhua County (TW); Chia Hong Lin, Hsinchu County (TW); Yu-Ting Lin, Hsin-Chu (TW); and Min-Feng Ku, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Mar. 30, 2023, as Appl. No. 18/192,745.
Claims priority of provisional application 63/413,677, filed on Oct. 6, 2022.
Claims priority of provisional application 63/393,599, filed on Jul. 29, 2022.
Prior Publication US 2024/0036108 A1, Feb. 1, 2024
Int. Cl. G01R 31/28 (2006.01); G01R 1/04 (2006.01); H01L 23/522 (2006.01); H01L 23/00 (2006.01)
CPC G01R 31/2896 (2013.01) [G01R 1/0441 (2013.01); H01L 23/5226 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a socket of a testing tool configured to provide testing signals;
a device-under-test (DUT) board configured to provide electrical routing; and
an integrated circuit (IC) die disposed between the socket and the DUT board, wherein the testing signals are electrically routed to the IC die through the DUT board, and wherein the IC die includes a substrate in which plurality of transistors is formed, a first structure that contains a plurality of first metallization components, and a second structure that contains a plurality of second metallization components, wherein the first structure is disposed over a first side of the substrate, and wherein the second structure is disposed over a second side of the substrate opposite the first side.