US 12,263,938 B1
Fault-tolerant multi-processor systems and methods for an aircraft
Scott Furman, Menlo Park, CA (US); Fernanda Aline Matta De Paiva, Los Altos Hills, CA (US); Sergio Henrique Soares Ferreira, San Jose, CA (US); Guy Bernard, Kirkland (CA); and Damien Bardon, San Jose, CA (US)
Assigned to Archer Aviation Inc., San Jose, CA (US)
Filed by Archer Aviation Inc., San Jose, CA (US)
Filed on Aug. 23, 2024, as Appl. No. 18/813,435.
Int. Cl. G06F 17/00 (2019.01); B64C 19/00 (2006.01); B64F 5/60 (2017.01)
CPC B64C 19/00 (2013.01) [B64F 5/60 (2017.01)] 30 Claims
OG exemplary drawing
 
1. A signal-processing multi-processor system for an aircraft, comprising:
a plurality of processors, wherein each processor is configured to perform operations comprising:
receiving, from a source processor among the plurality of the processors, a first copy of a signal corresponding to an input device;
sending a second copy of the signal to all other processors of the plurality excluding the source processor, wherein the second copy of the signal is substantially identical to the first copy of the signal;
receiving a number of second copies of the signal from all other processors of the plurality excluding the source processor, the number of second copies being equal to the number of all other processors of the plurality excluding the source processor;
determining a consensus signal based on the first copy and the second copies of the signal; and
determining a command signal for an effector of the aircraft based on the consensus signal, and
wherein no two processors of the plurality receive the signal from a same input device.