US 12,263,673 B2
Processing apparatus
Toshiyuki Kitazawa, Kanagawa (JP)
Assigned to Canon Kabushiki Kaisha, Tokyo (JP)
Filed by CANON KABUSHIKI KAISHA, Tokyo (JP)
Filed on May 17, 2022, as Appl. No. 17/746,185.
Claims priority of application No. 2021-084085 (JP), filed on May 18, 2021.
Prior Publication US 2022/0371342 A1, Nov. 24, 2022
Int. Cl. B41J 11/42 (2006.01); H03K 3/35 (2006.01)
CPC B41J 11/42 (2013.01) [H03K 3/35 (2013.01)] 5 Claims
OG exemplary drawing
 
1. A processing apparatus comprising:
an integrated circuit configured to operate as a controller that controls an interior of the processing apparatus;
a power supplier configured to be connected to an external power supply and to supply power to the integrated circuit;
a power switch configured to switch a state of the processing apparatus based on power supplied from the power supplier; and
a signal generation circuit configured as a latch circuit including a transistor, the signal generation circuit being connected to the integrated circuit and the power supplier, and
a storage unit configured to store a user setting,
wherein a first state of the signal generation circuit generates a first signal for causing the power supplier to supply power to the integrated circuit and a second state of the signal generation circuit generates a second signal for causing the power supplier to stop power supply to the integrated circuit, and
wherein the integrated circuit sets a terminal of the integrated circuit to control a level of a base terminal of the transistor included in the latch circuit,
wherein, if the user setting is a first setting, the integrated circuit is configured to, in a state that power is supplied to the integrated circuit from the power supplier, set the level of the base terminal of the transistor included in the latch circuit to cause the signal generation circuit to transition to the second state, and, if the user setting is a second setting, the integrated circuit is configured make a state of the integrated circuit transition to a sleep mode where power consumption is less than in a normal operation mode in which power supply to the integrated circuit is performed by the power supplier,
wherein, if the user setting is the first setting, the signal generation circuit transmits to the power supplier the second signal for causing the power supplier to stop power supply to the integrated circuit, and the power supplier stops power supply to the integrated circuit based on the second signal for causing the power supplier to stop power supply to the integrated circuit,
wherein the signal generation circuit is connected to the power switch, and
wherein, after power supply to the integrated circuit by the power supplier is stopped, based on an operation on the power switch, the signal generation circuit transitions to the first state and transmits to the power supplier the first signal for causing the power supplier to supply power to the integrated circuit, and the power supplier resumes power supply to the integrated circuit based on the first signal for causing the power supplier to supply power to the integrated circuit.