US 12,263,001 B2
Neural interface circuit for bidirectional signal transmission
Li Huang, Wuhan (CN); Cheng Huang, Wuhan (CN); Kai Li, Wuhan (CN); and Moutao Li, Wuhan (CN)
Assigned to WUHAN NEURACOM TECHNOLOGY DEVELOPMENT CO., LTD., Wuhan (CN)
Filed by WUHAN NEURACOM TECHNOLOGY DEVELOPMENT CO., LTD., Wuhan (CN)
Filed on Jul. 8, 2024, as Appl. No. 18/765,737.
Application 18/765,737 is a continuation of application No. PCT/CN2022/127283, filed on Oct. 25, 2022.
Claims priority of application No. 202210023507.3 (CN), filed on Jan. 10, 2022.
Prior Publication US 2024/0358309 A1, Oct. 31, 2024
Int. Cl. A61B 5/00 (2006.01); A61B 5/01 (2006.01); A61B 5/145 (2006.01); A61B 5/294 (2021.01)
CPC A61B 5/294 (2021.01) 3 Claims
OG exemplary drawing
 
1. A neural interface circuit for bidirectional signal transmission, comprising:
a plurality of electrodes configured to collect a neural signal and receive an excitation signal;
a plurality of sampling units, wherein each sampling unit comprises a plurality of collection input channels and a plurality of excitation output channels, the plurality of excitation output channels correspond to the plurality of collection input channels one by one, a collection input channel and a corresponding excitation output channel share a same electrode, the collection input channel is provided with a first gating switch, the first gating switch is connected to a control module, the control module is configured to control the first gating switch to be off or on to conduct the collection input channel; the excitation output channel comprises a second gating switch, the second gating switch is connected to the control module, the control module is configured to control the second gating switch be off or on to selectively conduct the excitation output channel;
wherein each collection input channel is further provided with a first signal processing unit, the first signal processing unit comprises a filtering circuit and an amplifying circuit, the filtering circuit is connected in series with the amplifying circuit; and the excitation output channel is further provided with a gain scaling and filtering denoising processing circuit;
an operational amplifier, wherein an output end of the collection input channel is connected to a non-inverting input end of the operational amplifier, an inverting input end of the operational amplifier is connected to an output end of the operational amplifier, and the output end of the operational amplifier is connected to an analog-to-digital (AD) conversion unit;
a sampling capacitor, wherein one end of the sampling capacitor is grounded, and another end of the sampling capacitor is connected to the non-inverting input end of the operational amplifier;
an output unit, wherein the output unit comprises a parallel-to-serial conversion module and a plurality of sampling output channels, input ends of the plurality of sampling output channels are connected to output ends of the plurality of sampling units in a one-to-one correspondence, output ends of the plurality of sampling output channels are connected to an input end of the parallel-to-serial conversion module, an output end of the parallel-to-serial conversion module is connected to the control module, each sampling output channel is connected in series with a third gating switch, the third gating switch is connected to the control module, and the control module is configured to control the third gating switch to be off or on; and
m sampling units disposed in a stacked manner, wherein each sampling unit is connected to n electrodes, there are m*n electrodes, m*n electrodes are configured to collect neural electrical signals to control the first gating switches S1˜Sn of each sampling unit to be conducted in sequence during sampling, the acquisition input channel is configured for sampling, and a sampled signal is converted into final digital data through AD conversion; m sampling units work simultaneously and output m data; each data is switched to output by controlling the third gating switch of each sampling output channel to be off or on, and a parallel-to-serial conversion is performed on the output data through a parallel-to-serial conversion module.