US 11,943,928 B2
Method for forming channel hole plug of three-dimensional memory device
Li Hong Xiao, Hubei (CN); Zhenyu Lu, Hubei (CN); Qian Tao, Hubei (CN); Yushi Hu, Hubei (CN); Jun Chen, Hubei (CN); LongDong Liu, Hubei (CN); and Meng Wang, Hubei (CN)
Assigned to Yangtze Memory Technologies Co., Ltd., Hubei (CN)
Filed by Yangtze Memory Technologies Co., Ltd., Hubei (CN)
Filed on Apr. 19, 2022, as Appl. No. 17/724,083.
Application 17/724,083 is a division of application No. 16/046,634, filed on Jul. 26, 2018, granted, now 11,309,327.
Application 16/046,634 is a continuation of application No. PCT/CN2018/083536, filed on Apr. 18, 2018.
Prior Publication US 2022/0238556 A1, Jul. 28, 2022
Int. Cl. H10B 43/27 (2023.01); H01L 21/28 (2006.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/35 (2023.01)
CPC H10B 43/27 (2023.02) [H01L 29/40114 (2019.08); H01L 29/40117 (2019.08); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/35 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method for forming a channel hole plug structure in a three-dimensional (3D) memory device, comprising:
forming an alternating dielectric stack disposed on a substrate;
forming an insulating layer and a hard mask layer on the alternating dielectric stack;
forming a channel structure, comprising:
forming a channel hole penetrating the insulating layer, the hard mask layer, and the alternating dielectric stack;
forming a functional layer on a sidewall of the channel hole; and
forming a channel layer covering at least a portion of the functional layer on the sidewall of the channel hole and in direct contact with a top surface of the hard mask layer;
removing a top portion of the channel structure and a portion of the insulating layer surrounding the top portion of the channel structure to form a recess; and
forming a channel hole plug in the recess, wherein a projection of the channel hole plug in a lateral plane covers a projection of the channel structure in the lateral plane.