CPC H10B 43/27 (2023.02) [H01L 21/76232 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H10B 41/27 (2023.02); H01L 24/08 (2013.01); H01L 2224/08145 (2013.01)] | 20 Claims |
1. A semiconductor device comprising:
a peripheral circuit structure including a first substrate and circuit elements on the first substrate;
a second substrate on the peripheral circuit structure;
a first horizontal conductive layer on the second substrate;
a second horizontal conductive layer on the first horizontal conductive layer;
a stack structure including a plurality of gate electrodes, stacked to be spaced apart from each other in a direction perpendicular to an upper surface of the second horizontal conductive layer, and a plurality of interlayer insulating layers stacked alternately with the plurality of gate electrodes;
a channel structure including a channel layer and penetrating through the first horizontal conductive layer, the second horizontal conductive layer, and the stack structure; and
a separation insulating layer penetrating through the first horizontal conductive layer, the second horizontal conductive layer, and the stack structure and extending in a first direction, the separation insulating layer including a first portion having a continuously decreasing width, and a second portion penetrating through the first and second horizontal conductive layers and having a width greater than a minimum width of the first portion, a sidewall of the second portion having a first slope from a bottom surface, the first slope intersecting a second slope which extends to a level of the first portion and the second portion intersecting, an intersection of the first slope and the second slope being less than 180 degrees.
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