US 11,943,921 B2
Embedded memory with improved fill-in window
Meng-Han Lin, Hsinchu (TW); Te-Hsin Chiu, Miaoli County (TW); and Wei Cheng Wu, Zhubei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jul. 27, 2022, as Appl. No. 17/874,416.
Application 16/574,247 is a division of application No. 16/051,721, filed on Aug. 1, 2018, granted, now 10,784,270, issued on Sep. 22, 2020.
Application 17/874,416 is a continuation of application No. 17/104,686, filed on Nov. 25, 2020, granted, now 11,488,971.
Application 17/104,686 is a continuation of application No. 16/574,247, filed on Sep. 18, 2019, granted, now 10,868,026, issued on Dec. 15, 2020.
Claims priority of provisional application 62/689,885, filed on Jun. 26, 2018.
Prior Publication US 2022/0367498 A1, Nov. 17, 2022
Int. Cl. H10B 41/44 (2023.01); H01L 21/027 (2006.01); H01L 21/28 (2006.01); H01L 21/3105 (2006.01); H01L 21/311 (2006.01); H01L 21/321 (2006.01); H01L 21/3213 (2006.01); H01L 21/762 (2006.01); H01L 21/768 (2006.01); H01L 21/8234 (2006.01); H01L 29/08 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01); H10B 41/30 (2023.01); H10B 41/35 (2023.01); H10B 41/41 (2023.01); H10B 41/42 (2023.01); H10B 43/40 (2023.01)
CPC H10B 41/44 (2023.02) [H01L 21/0276 (2013.01); H01L 21/28035 (2013.01); H01L 21/31053 (2013.01); H01L 21/31111 (2013.01); H01L 21/3212 (2013.01); H01L 21/32133 (2013.01); H01L 21/32139 (2013.01); H01L 21/76224 (2013.01); H01L 21/76802 (2013.01); H01L 29/0847 (2013.01); H01L 29/40114 (2019.08); H01L 29/42328 (2013.01); H01L 29/4916 (2013.01); H01L 29/66545 (2013.01); H01L 29/6656 (2013.01); H01L 29/66825 (2013.01); H01L 29/788 (2013.01); H10B 41/30 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) comprising:
a memory region and a logic region integrated in a substrate;
a plurality of memory cell structures disposed on the memory region, each memory cell structure of the plurality of memory cell structures comprising a control gate electrode disposed over the substrate, a select gate electrode disposed on one side of the control gate electrode, and a spacer between the control gate electrode and the select gate electrode;
a contact etch stop layer (CESL) disposed along an upper surface of the substrate, extending upwardly along the select gate electrode within the memory region; and
a lower inter-layer dielectric layer disposed on the CESL and fill between the plurality of memory cell structures within the memory region,
wherein the CESL is in direct contact with sidewalls of the select gate electrode and the lower inter-layer dielectric layer.