US 11,943,545 B2
Image processing device
Yutaka Murata, Tokyo (JP); Yoshinobu Tanaka, Tokyo (JP); Atsushi Ishihara, Tokyo (JP); and Akira Ueno, Tokyo (JP)
Assigned to OLYMPUS CORPORATION, Tokyo (JP)
Filed by OLYMPUS CORPORATION, Hachioji (JP)
Filed on Feb. 2, 2021, as Appl. No. 17/164,961.
Application 17/164,961 is a continuation of application No. PCT/JP2018/029572, filed on Aug. 7, 2018.
Prior Publication US 2021/0160425 A1, May 27, 2021
Int. Cl. H04N 23/80 (2023.01); G11C 11/413 (2006.01)
CPC H04N 23/80 (2023.01) [G11C 11/413 (2013.01)] 4 Claims
OG exemplary drawing
 
1. An image processing device comprising:
a circuit block in which an operation period is predetermined and intermittent operation is performed according to the operation period;
a plurality of SRAMs; and
a dummy control circuit configured to increase an intensity of a dummy operation of an unused SRAM among the plurality of SRAMs for a certain period of time before the operation period of the circuit block, and to decrease the intensity of the dummy operation of the unused SRAM among the plurality of SRAMs for a certain period of time after the operation period of the circuit block.