CPC H04N 19/61 (2014.11) [H04N 19/105 (2014.11); H04N 19/11 (2014.11); H04N 19/122 (2014.11); H04N 19/132 (2014.11); H04N 19/159 (2014.11); H04N 19/167 (2014.11); H04N 19/176 (2014.11); H04N 19/70 (2014.11)] | 21 Claims |
1. A method performed by a processor of a decoder, the method comprising:
determining a width and a height of a current block of a bitstream based on syntax elements in the bitstream;
determining whether the current block is an intra predicted block;
responsive to the current block being an intra predicted block, determining whether the intra predicted block is a matrix based intra prediction, MIP, predicted block;
responsive to the current block being a MIP predicted block, determining whether the MIP predicted block has one transform block or multiple transform blocks;
determining a MIP weight matrix to be used to decode the current block based on a MIP prediction mode of the current block;
responsive to determining that the MIP predicted block has one transform block:
deriving the MIP predicted block based on the MIP weight matrix and previously decoded elements in the bitstream; and
responsive to determining that the MIP predicted block has multiple transform blocks:
deriving a first MIP predicted block based on the MIP weight matrix and previously decoded elements in the bitstream; and
deriving remaining MIP predicted blocks based on the MIP weight matrix and previously decoded elements in the bitstream and decoded elements in at least one decoded transform block of the current block; and
outputting the MIP predicted block or the first MIP predicted block and remaining predicted blocks for subsequent processing by the decoder.
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