US 11,943,332 B2
Low depth AES SBox architecture for area-constraint hardware
Patrik Ekdahl, Dalby (SE); and Alexander Maximov, Lund (SE)
Assigned to Telefonaktiebolaget LM Ericsson (Publ), Stockholm (SE)
Appl. No. 17/604,210
Filed by TELEFONAKTIEBOLAGET LM ERICSSON (PUBL), Stockholm (SE)
PCT Filed Mar. 6, 2020, PCT No. PCT/EP2020/056065
§ 371(c)(1), (2) Date Oct. 15, 2021,
PCT Pub. No. WO2020/212016, PCT Pub. Date Oct. 22, 2020.
Claims priority of provisional application 62/834,359, filed on Apr. 15, 2019.
Prior Publication US 2022/0278822 A1, Sep. 1, 2022
Int. Cl. H04L 9/06 (2006.01)
CPC H04L 9/0631 (2013.01) [H04L 2209/122 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A substitution box (Sbox) circuit that performs an SBox computational step when comprised in cryptographic circuitry, the SBox circuit comprising:
a first circuit part comprising digital circuitry that generates a 4-bit first output signal (Y) from an 8-bit input signal (U);
a second circuit part, configured to operate in parallel with the first circuit part and to generate a 32-bit second output signal (L) from the 8-bit input signal (U), wherein the 32-bit second output signal (L) consists of four 8-bit sub-results; and
a third circuit part configured to produce four preliminary 8-bit results (K) by scalar multiplying each of the four 8-bit sub-results by a respective one bit of the 4-bit first output signal (Y), and to produce an 8-bit output signal (R) by summing the four preliminary 8-bit results (K),
wherein:
the first circuit part is configured to generate the 4-bit first output signal (Y) from the input signal (U) by performing a calculation that comprises a first linear matrix operation, a Galois Field (GF) multiplication, and a GF inversion; and
the second circuit part is configured to generate the second output signal (L) from the input signal (U) by performing a calculation that comprises a second linear matrix operation.