US 11,942,549 B2
Semiconductor device and method of manufacture
Wan-Yi Kao, Baoshan Township (TW); Yu-Cheng Shiau, Hsinchu (TW); Chunyao Wang, Zhubei (TW); Chih-Tang Peng, Zhubei (TW); Yung-Cheng Lu, Hsinchu (TW); and Chi On Chui, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Dec. 12, 2022, as Appl. No. 18/064,562.
Application 18/064,562 is a continuation of application No. 17/157,330, filed on Jan. 25, 2021, granted, now 11,527,653.
Claims priority of provisional application 63/055,045, filed on Jul. 22, 2020.
Prior Publication US 2023/0103640 A1, Apr. 6, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 21/762 (2006.01); H01L 21/8234 (2006.01); H01L 27/092 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/785 (2013.01) [H01L 21/0214 (2013.01); H01L 21/02211 (2013.01); H01L 21/02263 (2013.01); H01L 21/76224 (2013.01); H01L 21/76232 (2013.01); H01L 21/823481 (2013.01); H01L 27/0924 (2013.01); H01L 29/517 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/66818 (2013.01); H01L 21/76227 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, the method comprising:
lining a semiconductor fin with a first liner;
lining the semiconductor fin with a second liner different from the first liner;
lining the semiconductor fin with a third liner different from the second liner;
annealing the third liner to form silicon oxide;
lining the semiconductor fin with a fourth liner different from the third liner;
depositing a capping layer over the fourth liner;
annealing the capping layer to transform the capping layer to silicon oxide;
depositing a dielectric cap over the capping layer;
planarizing the dielectric cap to the semiconductor fin; and
exposing a sidewall of the semiconductor fin.