US 11,942,548 B2
Multi-gate device and method of fabrication thereof
Kuo-Cheng Ching, Hsinchu County (TW); Ching-Wei Tsai, Hsinchu (TW); Carlos H. Diaz, Los Altos Hills, CA (US); Chih-Hao Wang, Hsinchu County (TW); Wai-Yi Lien, Hsinchu (TW); and Ying-Keung Leung, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on May 18, 2021, as Appl. No. 17/302,987.
Application 17/302,987 is a continuation of application No. 16/722,905, filed on Dec. 20, 2019, granted, now 11,437,513.
Application 16/722,905 is a continuation of application No. 15/809,726, filed on Nov. 10, 2017, granted, now 10,516,049, issued on Dec. 24, 2019.
Application 15/809,726 is a continuation of application No. 14/788,161, filed on Jun. 30, 2015, granted, now 9,818,872, issued on Nov. 14, 2017.
Prior Publication US 2021/0273100 A1, Sep. 2, 2021
Int. Cl. H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/165 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/775 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/7848 (2013.01) [H01L 29/0649 (2013.01); H01L 29/0673 (2013.01); H01L 29/0676 (2013.01); H01L 29/165 (2013.01); H01L 29/42392 (2013.01); H01L 29/66439 (2013.01); H01L 29/66537 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/775 (2013.01); H01L 29/7851 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A multi-gate semiconductor device, comprising:
a fin element extending from a substrate;
a plurality of nanowire channel layers including a first nanowire channel layer, disposed over the fin element and a second nanowire channel layer over the first nanowire channel layer;
a first portion of a high-k gate dielectric material extending between the first nanowire channel layer and the second nanowire channel layer and a second portion of the high-k gate dielectric material extending between the first nanowire channel layer and the fin element;
a spacer layer adjacent the first portion of the high-k gate dielectric material and adjacent the second portion of the high-k gate dielectric material; and
a gate electrode disposed over the plurality of nanowire channel layers.