US 11,942,527 B2
Forming a cavity with a wet etch for backside contact formation
Yi-Hsiu Chen, Taipei (TW); and Andrew Joseph Kelly, Hengshan Township (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 26, 2022, as Appl. No. 17/873,210.
Application 17/873,210 is a continuation of application No. 17/097,468, filed on Nov. 13, 2020, granted, now 11,437,480.
Prior Publication US 2022/0359689 A1, Nov. 10, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/417 (2006.01); H01L 21/306 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/41791 (2013.01) [H01L 21/30608 (2013.01); H01L 29/0847 (2013.01); H01L 29/66545 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/66742 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated chip comprising:
a first source/drain region;
a second source/drain region spaced apart from the first source/drain region;
a channel structure extending between the first source/drain region and the second source/drain region;
a gate electrode arranged over the channel structure;
a first backside contact arranged below and coupled to the first source/drain region;
a backside dielectric extending laterally from a sidewall of the first backside contact and covering an entire lower surface of the second source/drain region; and
a first upper interconnect contact arranged over and coupled to the second source/drain region.