| CPC H01L 27/0924 (2013.01) [H01L 21/823412 (2013.01); H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 21/823481 (2013.01); H01L 29/0653 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01)] | 20 Claims |
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1. A method comprising:
forming a fin structure over a substrate, wherein the fin structure comprises first semiconductor layers and second semiconductor layers alternately stacked;
depositing an isolation structure over the substrate;
forming a dummy gate structure over the fin structure;
removing a portion of the fin structure uncovered by the dummy gate structure;
growing a source/drain epitaxial structure on a side of remaining portions of the second semiconductor layers;
replacing the dummy gate structure and the first semiconductor layers with a metal gate structure;
removing the substrate to expose a bottom surface of the isolation structure;
forming an opening in the isolation structure and exposing a gate electrode of the metal gate structure;
forming a gate via in the opening such that the gate via is connected to the metal gate structure and embedded in the isolation structure; and
forming a spacer structure in the opening prior to forming the gate via.
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