| CPC H01L 27/0924 (2013.01) [H01L 21/823431 (2013.01); H01L 21/823468 (2013.01); H01L 29/6656 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01)] | 20 Claims |
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1. A method, comprising:
forming first, second and third fins from a substrate, wherein the first fin includes a first plurality of semiconductor layers, the second fin includes a second plurality of semiconductor layers, and the third fin includes a third plurality of semiconductor layers, and wherein each of the first, second, and third plurality of semiconductor layers comprises first semiconductor layers and second semiconductor layers;
forming a first dielectric feature between the first fin and the second fin, wherein the first dielectric feature has a first dielectric layer and a second dielectric layer in contact with sidewalls and a bottom of the first dielectric layer;
forming a second dielectric feature between the second fin and the third fin, wherein the second dielectric feature has a third dielectric layer and a fourth dielectric layer in contact with sidewalls and a bottom of the third dielectric layer;
forming a sacrificial gate stack on a portion of the first, second, third fins, the first dielectric feature, and the second dielectric feature, wherein a portion of the first, second, third fins, first dielectric feature, and second dielectric feature are exposed;
removing a portion of the exposed portions of the first, second, and third fins not covered by the sacrificial gate stack;
removing the exposed portion of the second and fourth dielectric layers;
lateral recessing the second and fourth dielectric layers;
forming a dielectric spacer under the first and third dielectric layers and in space created by the lateral recessing of the second and fourth dielectric layers; and
removing the sacrificial gate stack to expose portions of the first, second, and third fins.
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