US 11,942,463 B2
Semiconductor devices
Hyun Mog Park, Seoul (KR); and Sang Youn Jo, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Apr. 28, 2023, as Appl. No. 18/140,917.
Application 18/140,917 is a continuation of application No. 17/687,790, filed on Mar. 7, 2022, granted, now 11,664,362.
Application 17/687,790 is a continuation of application No. 16/994,207, filed on Aug. 14, 2020, granted, now 11,270,987, issued on Mar. 8, 2022.
Application 16/994,207 is a continuation of application No. 16/414,083, filed on May 16, 2019, granted, now 10,748,886, issued on Aug. 18, 2020.
Claims priority of application No. 10-2018-0116806 (KR), filed on Oct. 1, 2018.
Prior Publication US 2023/0268333 A1, Aug. 24, 2023
Int. Cl. H01L 25/18 (2023.01); H01L 23/00 (2006.01); H01L 23/528 (2006.01); H01L 25/00 (2006.01); H10B 41/27 (2023.01); H10B 41/30 (2023.01); H10B 41/40 (2023.01); H10B 43/27 (2023.01); H10B 43/30 (2023.01); H10B 43/40 (2023.01)
CPC H01L 25/18 (2013.01) [H01L 23/528 (2013.01); H01L 24/05 (2013.01); H01L 24/08 (2013.01); H01L 24/09 (2013.01); H01L 24/89 (2013.01); H01L 25/50 (2013.01); H10B 41/27 (2023.02); H10B 41/30 (2023.02); H10B 41/40 (2023.02); H10B 43/27 (2023.02); H10B 43/30 (2023.02); H10B 43/40 (2023.02); H01L 2224/0557 (2013.01); H01L 2224/08147 (2013.01); H01L 2224/0913 (2013.01); H01L 2224/80001 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first substrate structure including a first substrate, gate electrodes stacked and separated from each other in a first direction, perpendicular to a first surface of the first substrate, and extended by different lengths in a second direction, parallel to the first surface of the first substrate, to provide contact regions, cell contact plugs extending in the first direction and connected to the gate electrodes in the contact regions, and first bonding pads disposed on the cell contact plugs to be electrically connected to the cell contact plugs, respectively; and
a second substrate structure, connected to the first substrate structure on the first substrate structure, and including a second substrate, circuit elements disposed on the second substrate and electrically connected to the gate electrodes, and second bonding pads disposed on the circuit elements to correspond to the first bonding pads and bonded to the first bonding pads,
wherein, in the first substrate structure, the contact regions include a first group of contact regions each having a first width in the second direction and a second group of contact regions, wherein for each contact region of the second group, at least a portion of the contact region vertically overlaps at least one first bonding pad, and the contact region has a second width in the second direction greater than the first width, and the second width is greater than a width of the at least one first bonding pad,
the first substrate structure further includes channels passing through the gate electrodes and extending perpendicularly to the first substrate, bit lines electrically connected to the channels, and third bonding pads disposed to be electrically connected to the bit lines,
the second substrate structure further includes fourth bonding pads bonded to the third bonding pads, and
the third bonding pads have a size substantially the same as a size of the first bonding pads.