US 11,942,452 B2
Semiconductor module arrangement
Christian Robert Mueller, Schweinfurt (DE); Andressa Colvero Schittler, Soest (DE); Daniel Domes, Ruethen (DE); and Andre Lenze, Warstein (DE)
Assigned to Infineon Technologies AG, Neubiberg (DE)
Filed by Infineon Technologies AG, Neubiberg (DE)
Filed on Jul. 27, 2020, as Appl. No. 16/939,130.
Claims priority of application No. 19190491 (EP), filed on Aug. 7, 2019.
Prior Publication US 2021/0043605 A1, Feb. 11, 2021
Int. Cl. H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 23/049 (2006.01); H01L 23/367 (2006.01); H01L 23/538 (2006.01); H01L 23/64 (2006.01)
CPC H01L 25/0655 (2013.01) [H01L 23/049 (2013.01); H01L 23/367 (2013.01); H01L 23/5383 (2013.01); H01L 23/642 (2013.01); H01L 24/48 (2013.01); H01L 2224/48225 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A semiconductor module arrangement, comprising:
a housing;
a first semiconductor substrate arranged inside the housing;
a second semiconductor substrate arranged inside the housing;
a first plurality of controllable semiconductor elements; and
a second plurality of controllable semiconductor elements,
wherein:
during operation of the semiconductor module arrangement, each controllable semiconductor element of the first plurality of controllable semiconductor elements generates switching losses and conduction losses, the switching losses being greater than the conduction losses;
during operation of the semiconductor module arrangement, each controllable semiconductor element of the second plurality of controllable semiconductor elements generates switching losses and conduction losses, the conduction losses being greater than the switching losses;
at least a first sub-group of the first plurality of controllable semiconductor elements is arranged on the first semiconductor substrate; and
at least a first sub-group of the second plurality of controllable semiconductor elements is arranged on the second semiconductor substrate.