US 11,942,448 B2
Integrated circuit die pad cavity
Bo-Hsun Pan, New Taipei (TW); Hung-Yu Chou, Taipei (TW); Chung-Hao Lin, Taipei (TW); and Yuh-Harng Chien, New Taipei (TW)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Jul. 16, 2021, as Appl. No. 17/377,719.
Prior Publication US 2023/0016577 A1, Jan. 19, 2023
Int. Cl. H01L 21/56 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/28 (2006.01)
CPC H01L 24/48 (2013.01) [H01L 21/4828 (2013.01); H01L 21/565 (2013.01); H01L 23/28 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48177 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A method of fabricating integrated circuits, the method comprising:
providing an electrically conductive die pad having a generally planar top surface;
etching a cavity in the electrically conductive die pad;
attaching a die on the electrically conductive die pad;
attaching a wire bond from the die to a bottom surface of the cavity; and
forming a mold compound over the die and in the cavity.