US 11,942,391 B2
System in package with flip chip die over multi-layer heatsink stanchion
Kelly M. Lear, Longwood, FL (US); Jeffrey Miller, Allen, TX (US); Mihir Roy, Sachse, TX (US); and Christine Blair, Lewisville, TX (US)
Assigned to Qorvo US, Inc., Greensboro, NC (US)
Filed by Qorvo US, Inc., Greensboro, NC (US)
Filed on Nov. 30, 2021, as Appl. No. 17/538,583.
Prior Publication US 2023/0170275 A1, Jun. 1, 2023
Int. Cl. H01L 23/367 (2006.01); H01L 23/48 (2006.01); H01L 23/492 (2006.01)
CPC H01L 23/3677 (2013.01) [H01L 23/481 (2013.01); H01L 23/4924 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a chiplet having a first substrate and a first die, wherein:
the first substrate includes a plurality of first dielectric layers and at least one first heatsink stanchion extending through the plurality of first dielectric layers, wherein:
the at least one first heatsink stanchion includes a plurality of first heatsink metal plates and a plurality of first heatsink metal bars, which is vertically alternated with the plurality of first heatsink metal plates; and
the plurality of first heatsink metal bars includes at least three first heatsink metal bars and is configured in a layered-cake shape, such that horizontal sizes of the at least three first heatsink metal bars increase from top to bottom within the at least one first heatsink stanchion; and
the first die is deposed over the first substrate and connected to the at least one first heatsink stanchion, such that heat generated by the first die can be dissipated by the at least one first heatsink stanchion within the first substrate; and
a second substrate, wherein:
the second substrate includes a plurality of second dielectric layers and at least one second heatsink stanchion extending through the plurality of second dielectric layers, wherein:
the at least one second heatsink stanchion includes a plurality of second heatsink metal plates and a plurality of second heatsink metal bars, which is alternated with the plurality of second heatsink metal plates; and
the plurality of second heatsink metal bars of the second substrate is configured in a layered-cake shape; and
the chiplet is deposed over the second substrate, wherein the at least one first heatsink stanchion of the first substrate is connected to the at least one second heatsink stanchion of the second substrate by at least one package interconnect, such that the heat generated by the first die can be propagated through the at least one first heatsink stanchion of the first substrate and the at least one second heatsink stanchion of the second substrate.