US 11,942,377 B2
Gate structure and patterning method
Lung-Kun Chu, New Taipei (TW); Mao-Lin Huang, Hsinchu (TW); Wei-Hao Wu, Hsinchu (TW); and Kuo-Cheng Chiang, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Feb. 28, 2022, as Appl. No. 17/682,298.
Application 17/682,298 is a division of application No. 16/381,232, filed on Apr. 11, 2019, granted, now 11,264,288.
Claims priority of provisional application 62/738,670, filed on Sep. 28, 2018.
Prior Publication US 2022/0181218 A1, Jun. 9, 2022
Int. Cl. H01L 29/40 (2006.01); H01L 21/3213 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/423 (2006.01)
CPC H01L 21/823842 (2013.01) [H01L 21/32134 (2013.01); H01L 21/823821 (2013.01); H01L 27/0924 (2013.01); H01L 29/401 (2013.01); H01L 29/42372 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a semiconductor substrate;
a plurality of channel regions, including a p-type channel region, an n-type channel region, and a third channel region disposed over the semiconductor substrate; and
a gate structure comprising:
a gate dielectric layer disposed over the plurality of channel regions;
a work function metal (WFM) structure disposed over the gate dielectric layer, wherein the WFM structure includes an n-type WFM layer over the n-type channel region and not over the p-type channel region or the third channel region and further includes a p-type WFM layer over both the n-type WFM layer and the p-type channel region and not the third channel region; and
a fill metal layer.