US 11,942,372 B2
Dielectric protection layer in middle-of-line interconnect structure manufacturing method
Kuan-Da Huang, Hsinchu County (TW); Hao-Heng Liu, Hsinchu (TW); and Li-Te Lin, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 27, 2021, as Appl. No. 17/459,065.
Prior Publication US 2023/0061082 A1, Mar. 2, 2023
Int. Cl. H01L 21/8234 (2006.01); H01L 27/02 (2006.01); H01L 27/088 (2006.01)
CPC H01L 21/823475 (2013.01) [H01L 21/823437 (2013.01); H01L 21/823462 (2013.01); H01L 27/0207 (2013.01); H01L 27/088 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for manufacturing an integrated chip, comprising:
forming a transistor structure over a substrate, wherein the transistor structure comprises a pair of source/drain regions and a gate electrode between the source/drain regions;
forming a lower inter-level dielectric (ILD) layer over the pair of source/drain regions and around the gate electrode;
forming a gate capping layer over the gate electrode; and
performing a selective etch and deposition process to form a dielectric protection layer on the gate capping layer while forming a contact opening within the lower ILD layer; and
forming a lower source/drain contact within the contact opening.