US 11,942,183 B2
Adaptive write operations for a memory device
Mattia Boniardi, Cormano (IT); Richard K. Dodge, Santa Clara, CA (US); Innocenzo Tortorelli, Cernusco Sul Naviglio (IT); Mattia Robustelli, Milan (IT); and Mario Allegra, Monza (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 15, 2021, as Appl. No. 17/502,481.
Application 17/502,481 is a division of application No. 16/518,876, filed on Jul. 22, 2019, granted, now 11,158,358.
Prior Publication US 2022/0108732 A1, Apr. 7, 2022
Int. Cl. G11C 7/00 (2006.01); G11C 7/10 (2006.01)
CPC G11C 7/1096 (2013.01) [G11C 7/1051 (2013.01)] 17 Claims
OG exemplary drawing
 
14. A memory system, comprising:
one or more memory arrays; and
one or more controllers coupled with the one or more memory arrays and configured to cause the memory system to:
perform one or more first write operations on the one or more memory arrays according to a first pulse magnitude and a first pulse duration;
identify that a quantity of access operations performed on the one or more memory arrays satisfies a threshold; and
perform, based at least in part on identifying that the quantity of access operations performed on the one or more memory arrays satisfies the threshold, one or more second write operations on the one or more memory arrays according to a second pulse magnitude and a second pulse duration, wherein the second pulse magnitude is greater than the first pulse magnitude, and the second pulse duration is shorter than the first pulse duration.