US 11,942,173 B2
Memory apparatus and semiconductor system including the same
Heeeun Choi, Icheon-si (KR); and Yeong Han Jeong, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Sep. 13, 2021, as Appl. No. 17/473,299.
Claims priority of application No. 10-2021-0050403 (KR), filed on Apr. 19, 2021.
Prior Publication US 2022/0336035 A1, Oct. 20, 2022
Int. Cl. G11C 29/42 (2006.01); G11C 29/00 (2006.01); G11C 29/18 (2006.01); G11C 29/36 (2006.01)
CPC G11C 29/42 (2013.01) [G11C 29/18 (2013.01); G11C 29/36 (2013.01); G11C 29/785 (2013.01); G11C 2029/1802 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A memory apparatus comprising:
an address decoding circuit configured to output a test redundancy address based on an address that is transmitted from a memory controller; and
a redundancy address check circuit configured to determine whether the test redundancy address is replacing a failed address by comparing the test redundancy address with a reference address, in an ECC test operation,
wherein the reference address is a redundancy address that was most recently used to replace a failed address.