US 11,942,167 B2
Fuse array layout pattern and related apparatuses, systems, and methods
Wei Lu Chu, Shanghai (CN); Jing Wang, Shanghai (CN); Zhiwei Liang, Shanghai (CN); and Raghu Sreeramaneni, Telangana (IN)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Feb. 24, 2020, as Appl. No. 16/799,011.
Prior Publication US 2021/0264997 A1, Aug. 26, 2021
Int. Cl. G11C 17/18 (2006.01); G11C 17/16 (2006.01); H10B 20/20 (2023.01)
CPC G11C 17/16 (2013.01) [G11C 17/18 (2013.01); H10B 20/20 (2023.02)] 8 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a fuse, comprising:
a gate comprising electrically conductive material;
an active material comprising a doped semiconductor material;
the gate overlapping the active material to define an overlap therebetween; and
the overlap of the active material by the gate defined by a triangular shape.