US 11,942,140 B2
Nonvolatile memory devices
Hee-Woong Kang, Suwon-si (KR); Dong-Hun Kwak, Hwaseong-si (KR); Jun-Ho Seo, Hwaseong-si (KR); and Hee-Won Lee, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Oct. 1, 2022, as Appl. No. 17/958,386.
Application 16/183,315 is a division of application No. 15/604,406, filed on May 24, 2017, granted, now 10,153,029, issued on Dec. 11, 2018.
Application 17/958,386 is a continuation of application No. 17/321,393, filed on May 14, 2021, granted, now 11,462,260, issued on Oct. 4, 2022.
Application 17/321,393 is a continuation of application No. 16/991,693, filed on Aug. 12, 2020, granted, now 11,017,838, issued on May 25, 2021.
Application 16/991,693 is a continuation in part of application No. 16/817,951, filed on Mar. 13, 2020, granted, now 10,777,254, issued on Sep. 15, 2020.
Application 16/817,951 is a continuation of application No. 16/675,331, filed on Nov. 6, 2019, granted, now 10,672,454, issued on Jun. 2, 2020.
Application 16/675,331 is a continuation of application No. 16/183,315, filed on Nov. 7, 2018, granted, now 10,629,254, issued on Apr. 21, 2020.
Claims priority of application No. 10-2016-0099219 (KR), filed on Aug. 4, 2016.
Prior Publication US 2023/0036205 A1, Feb. 2, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 7/10 (2006.01); G11C 7/12 (2006.01); G11C 8/12 (2006.01); G11C 11/4074 (2006.01); G11C 11/408 (2006.01); G11C 11/4097 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/06 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/30 (2006.01); G11C 16/34 (2006.01)
CPC G11C 11/4074 (2013.01) [G11C 7/109 (2013.01); G11C 7/12 (2013.01); G11C 8/12 (2013.01); G11C 11/4082 (2013.01); G11C 11/4085 (2013.01); G11C 11/4097 (2013.01); G11C 11/5628 (2013.01); G11C 16/0483 (2013.01); G11C 16/06 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/30 (2013.01); G11C 16/3436 (2013.01); G11C 2207/2209 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A nonvolatile memory device comprising:
a memory cell region including a first metal pad;
a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad;
a memory cell array in the memory cell region, the memory cell array including a plurality of mats corresponding to different word-lines, each of the plurality of mats including a plurality of cell strings connected to a plurality of word-lines, a plurality of bit-lines, a plurality of string selection lines and a ground selection line, wherein:
a first cell string of a first mat of the plurality of mats is connected to a plurality of first word-lines, a first bit-line, a first string selection line and a first ground selection line,
a second cell string of a second mat of the plurality of mats is connected to a plurality of second word-lines, a second bit-line, a second string selection line and a second ground selection line,
the first and second cell strings are perpendicular to a substrate respectively, and
each of the first and second cell strings includes at least one ground selection transistor, a plurality of memory cells, and a plurality of string selection transistors coupled in series; and
a row decoder in the peripheral circuit region, the row decoder connected to the plurality of first and second word-lines and configured to apply corresponding word-line voltages to the plurality of first and second word-lines through the first metal pad and the second metal pad,
wherein the row decoder is configured to:
apply a first voltage to a third word-line among the plurality of first and second word-lines when a read operation of the nonvolatile memory device is performed for only one of the first and second mats, and
apply a second voltage greater than the first voltage to the third word-line when the read operation is performed for both of the first and second mats simultaneously.