| CPC G09G 3/2092 (2013.01) [G09G 2300/0426 (2013.01); G09G 2310/0275 (2013.01); G09G 2310/0297 (2013.01); G09G 2310/08 (2013.01)] | 19 Claims |
|
1. A display device comprising a display panel comprising:
a data driver that converts input data into a data signal and supplies the data signal to an output line;
a pixel unit including a plurality of pixels that display an image based on the data signal;
a demultiplexer including a plurality of transistors electrically connected to the output line in the display panel, and transmitting the data signal from the output line to data lines electrically connected to the plurality of pixels; and
a timing controller that supplies control signals to control a supply timing of the data signal, wherein
the plurality of transistors include a first transistor, a second transistor, a third transistor, and a fourth transistor,
the first transistor and the second transistor are electrically connected in parallel,
the third transistor and the fourth transistor are electrically connected in parallel,
the first transistor and the third transistor are electrically connected in parallel,
the second transistor and the fourth transistor are electrically connected in parallel, and
the first transistor, the second transistor, the third transistor, and the fourth transistor are electrically connected between the output line and a data line among the data lines,
wherein the demultiplexer comprises a first distributor that outputs the data signal to a first data line in response to a first control signal supplied to a first control line,
wherein the first distributor comprises:
the first transistor including a first gate electrode;
the second transistor including a second gate electrode and disposed in a first direction with respect to the first transistor;
the third transistor including a third gate electrode and disposed in a second direction intersecting the first direction with respect to the first transistor; and
the fourth transistor including a fourth gate electrode and disposed in the first direction with respect to the third transistor,
wherein the display panel comprises:
an active layer disposed on a base substrate, the active layer including a channel region;
a gate insulating layer disposed on the active layer; and
a first conductive layer disposed on the gate insulating layer, and
wherein the first conductive layer comprises:
a first portion overlapping the active layer, extending in the second direction, and forming the first gate electrode and the third gate electrode;
a second portion overlapping the active layer, spaced apart from the first portion, extending in the second direction, and forming the second gate electrode and the fourth gate electrode; and
a first connection portion that does not overlap the active layer, and electrically connecting an end of the first portion and an end of the second portion of the first conductive layer.
|