US 11,941,742 B2
Tiled processor communication fabric
Adam J. Smith, St Albans (GB); Sergio V. Tota, London (GB); Christopher G. Martin, Cupertino, CA (US); Yoong Chert Foo, Greater London (GB); Terence M. Potter, Austin, TX (US); and Max J. Batley, London (GB)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Jun. 23, 2022, as Appl. No. 17/808,392.
Prior Publication US 2023/0419585 A1, Dec. 28, 2023
Int. Cl. G06T 15/00 (2011.01); G06F 9/38 (2018.01)
CPC G06T 15/005 (2013.01) [G06F 9/3887 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising a processor that includes:
multiple client circuits;
fabric circuitry that includes at least first and second instances of a tile, wherein the tile includes:
client inputs configured to interface with client circuits;
tile inputs configured to interface with one or more other tile instances; and
communication resources assignable to the client inputs and tile inputs, wherein the communication resources include:
multiple internal links;
client outputs configured to interface with client circuits; and
tile outputs configured to interface with one or more other tile instances;
control circuitry configured to:
in a given cycle, assign communication resources of a given tile instance to at least a portion of the client inputs and tile inputs for a next cycle based on priority information for the tile instance's inputs; and
update priority information for a given tile instance of the fabric circuitry based on assignment results over multiple cycles.