CPC G06N 3/04 (2013.01) [G06F 16/00 (2019.01); G06N 3/08 (2013.01)] | 7 Claims |
1. An information processing apparatus comprising:
a memory circuit; and
a processor circuit coupled to the memory circuit, the processor circuit being configured to:
convert learning data stored in the memory circuit into a first mini-batch by automatically performing data extension processing on the learning data, the data extension processing including automatically extracting a first portion area at randomly determined position and range from a whole of the learning data and automatically resizing the extracted first portion area to a predetermined size;
perform first learning processing on a weight parameter of each layer in a neural network by using the first mini-batch;
determine whether a predetermined condition is satisfied in the performing of the first learning processing;
in a case where the predetermined condition is satisfied in the performing of the first learning processing, automatically convert the learning data into a second mini-batch without performing the data extension processing on the learning data, the converting of the learning data without performing the data extension processing including automatically resizing whole of the learning data into the predetermined size and automatically extracting a second portion area at predetermined position and range from among whole of the resized learning data, and
automatically perform, using the second mini-batch, second learning processing on the weight parameter of each layer in the neural network on which the first learning processing has been performed using the first mini-batch;
input inference data stored in the memory circuit into the neural network on which the second learning processing has been performed using the second mini-batch; and
output an inference result obtained by the inputting of the inference data to the neural network.
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