US 11,941,399 B2
Exposing valid byte lanes as vector predicates to CPU
Joseph Zbiciak, San Jose, CA (US); and Son H. Tran, Murphy, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Mar. 7, 2022, as Appl. No. 17/687,780.
Application 17/687,780 is a continuation of application No. 15/635,449, filed on Jun. 28, 2017, granted, now 11,269,638.
Prior Publication US 2022/0197637 A1, Jun. 23, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/30 (2018.01); G06F 9/35 (2018.01); G06F 9/38 (2018.01)
CPC G06F 9/3016 (2013.01) [G06F 9/3004 (2013.01); G06F 9/3013 (2013.01); G06F 9/35 (2013.01); G06F 9/3851 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a memory configured to store a first data vector;
a processor that includes:
a functional unit configured to operate on the first data vector;
a vector register file; and
a predicate register file; and
a memory controller coupled between the processor and the memory that includes:
a head register; and
a valid register, wherein the memory controller is configured to:
retrieve the first data vector from the memory;
produce a second data vector that includes the first data vector;
store an element of the second data vector in the head register;
store a valid bit associated with the second data vector in the valid register; and
in response to a read instruction from the processor, cause the element of the second data vector to be stored in the vector register file and the valid bit to be stored in the predicate register file.