US 11,941,339 B1
Automated equal-resistance routing in compact pattern
Linx Lin, New Taipei (TW); Alex Tsai, Taipei (TW); and Hung-Shih Wang, Hsinchu County (TW)
Assigned to Synopsys, Inc., Mountain View, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Feb. 24, 2022, as Appl. No. 17/679,679.
Claims priority of provisional application 63/154,637, filed on Feb. 26, 2021.
Int. Cl. G06F 30/3953 (2020.01); G06F 30/394 (2020.01); G06F 30/3947 (2020.01); G06F 30/398 (2020.01); G06F 119/02 (2020.01)
CPC G06F 30/3953 (2020.01) [G06F 30/394 (2020.01); G06F 30/3947 (2020.01); G06F 30/398 (2020.01); G06F 2119/02 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method for generating a routing for an integrated circuit (IC) design, the method comprising:
receiving information describing a set of pin-pairs of an integrated circuit (IC) design;
determining, by a processor, an initial routing of the IC design by (i) defining connected wires between each pin-pair in the set of pin-pairs, and (ii) evaluating a target resistance for the pin-pair over the connected wires, wherein each connected wire is routed with other connected wires;
determining, by the processor, after initial routing, a resistance adjustment to be applied to adjust wire resistance of the connected wires, the resistance adjustment being based on a square routing in response to a wire resistance being below the target resistance, and the resistance adjustment being based on a multi-layer stacking in response to the wire resistance being above the target resistance; and
providing routing in patterns as generated by the initial routing and the resistance adjustment.