US 11,941,338 B2
Integrated circuit with dummy boundary cells
Wei-Yi Hu, Zhubei (TW); Chih-Ming Chao, Hsinchu (TW); and Chi-Yeh Yu, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 26, 2022, as Appl. No. 17/873,699.
Application 17/873,699 is a division of application No. 16/885,657, filed on May 28, 2020, granted, now 11,443,094.
Claims priority of provisional application 62/883,743, filed on Aug. 7, 2019.
Prior Publication US 2022/0358276 A1, Nov. 10, 2022
Int. Cl. G06F 30/392 (2020.01); G06F 30/398 (2020.01); H01L 27/02 (2006.01); H01L 29/423 (2006.01); G06F 115/08 (2020.01)
CPC G06F 30/392 (2020.01) [G06F 30/398 (2020.01); H01L 27/0207 (2013.01); H01L 29/42376 (2013.01); G06F 2115/08 (2020.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC), comprising:
a plurality of macros, each comprising a macro boundary and a main pattern surrounded by the macro boundary; and
a top channel comprising a plurality of first sub-channels and a plurality of second sub-channels,
wherein each of the first sub-channels is arranged between a first macro and a second macro of the macros, and is formed by a plurality of first dummy boundary cells,
wherein each of the second sub-channels is arranged between two of the second macros, and is formed by a plurality of second dummy boundary cells,
wherein the macro boundaries of the first macros are formed by the first dummy boundary cells, and the macro boundaries of the second macros are formed by the second dummy boundary cells,
wherein a first gate length of dummy patterns within the first dummy boundary cells is greater than a second gate length of dummy patterns within the second dummy boundary cells, and the first and second dummy boundary cells are the same size.