US 11,940,918 B2
Memory pipeline control in a hierarchical memory system
Abhijeet Ashok Chachad, Plano, TX (US); Timothy David Anderson, University Park, TX (US); Kai Chirca, Dallas, TX (US); and David Matthew Thompson, Dallas, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Feb. 13, 2023, as Appl. No. 18/167,921.
Application 18/167,921 is a continuation of application No. 17/492,776, filed on Oct. 4, 2021, granted, now 11,580,024.
Application 17/492,776 is a continuation of application No. 16/879,264, filed on May 20, 2020, granted, now 11,138,117, issued on Oct. 5, 2021.
Claims priority of provisional application 62/852,480, filed on May 24, 2019.
Prior Publication US 2023/0185719 A1, Jun. 15, 2023
Int. Cl. G06F 12/00 (2006.01); G06F 1/14 (2006.01); G06F 9/54 (2006.01); G06F 12/0811 (2016.01); G06F 12/0842 (2016.01); G06F 12/0888 (2016.01)
CPC G06F 12/0842 (2013.01) [G06F 1/14 (2013.01); G06F 9/544 (2013.01); G06F 12/0811 (2013.01); G06F 12/0888 (2013.01); G06F 2212/1016 (2013.01)] 20 Claims
OG exemplary drawing
 
15. A method comprising:
receiving, by a cache controller, a first transaction, wherein the cache controller includes a pipeline configured to write to a memory and a bypass path that is coupled in parallel with the pipeline;
determining whether the first transaction is associated with a write to the memory;
based on the first transaction not being associated with the write to the memory, determine when to provide the first transaction to the bypass path based on whether a second transaction is in the pipeline; and
providing the first transaction to the bypass path.